FROM TAPE: Press ▶ PLAY, then key FROM TAPE + XXXX + GO EXECTO TAPE: Press ● REC, then key TO TAPE + XXXX + ADRSSSSS + ADRSEEEE + GO EXEC
ABC-80 Microcomputer Learning Kit Guide
Keypad Controls & PC Keyboard Mapping
ABC-80 Key
PC Key
Function Description
0 – 9, A – F
0–9, A–F
Hexadecimal address & data input
ADRS
A / M
Set / examine memory address (A3 A2 A1 A0)
DATA
D
Set / examine memory byte data (D1 D0)
+ (NEXT)
+ / →
Increment address and display next byte
- (STEP)
- / F10
Single-step decrement / execute instruction
GO EXEC
Enter / G
Execute program starting at current address
RST
Escape
Hardware CPU Reset vector jump (0000H)
TO TAPE
W
Write/save memory block to cassette audio tape
FROM TAPE
L
Read/load program from cassette audio tape
Inspector Execution Controls
Control
PC Key
Function Description
Run
F5
Resume continuous emulation
Pause
F6
Freeze the CPU at the next instruction boundary
Step
F7 / Space
Execute exactly one instruction (while paused)
Reset CPU
Escape
Reset the CPU to 0000H
USER'S MANUAL
ABC-80 Microcomputer Operating Manual & Cassette Program Book
Chapter 1 of 8
CHAPTER 1
Introduction & System Overview
Historical heritage, system architecture, CPU timing, memory banking, and dual Intel 8255A Programmable Peripheral Interfaces.
1.1 Historical Heritage of the ABC-80 Microcomputer
The ABC-80 Educational Microcomputer Learning Kit was manufactured in Taiwan during the early 1980s as the definitive training system for universities, technical colleges, and vocational institutions teaching 8-bit microprocessors, assembly language, and hardware interfacing. Accompanied by the classic textbook 《Z80 微電腦入門 — 原理與應用程式》, it enabled an entire generation of engineers to learn machine architecture through tactile, hands-on experimentation.
1.2 System Block Diagram & Architecture
The ABC-80 is organized around the classic Zilog Z80A 8-bit CPU, communicating with memory and I/O devices over an isolated 16-bit address bus (A0–A15), an 8-bit bidirectional data bus (D0–D7), and an active-low control bus (/MREQ, /IORQ, /RD, /WR, /M1, /WAIT, /RESET).
Hardware programmer for 2716 / 2732 UV-erasable EPROMs
1.3 Master Clock & Instruction T-States
The master clock oscillator uses a standard 3.579545 MHz NTSC colorburst crystal (XTAL1) buffered through a 74LS04 inverter stage and divided by two via a 74LS74 dual D-type flip-flop (U12). This delivers a symmetrical 1.7897725 MHz clock (nominal 1.79 MHz) to the Z80 CLK pin (pin 6). Each clock cycle (T-state) has a duration of:
Basic Z80 instructions require 4 T-states for opcode fetch (M1 cycle: 2.235 μs). Internal register-to-register operations take 4 T-states, while memory read/write cycles require 7 to 11 T-states. Delay subroutines in the Monitor ROM are mathematically calibrated against this exact frequency.
The ABC-80 hardware map allocates the lower 4KB (0000H–0FFFH) to ROM and the range 1000H–FFFFH to RAM. On cold reset, the Monitor ROM executes the ramchk routine at 06DCH: it writes test bit patterns (55H / AAH) to ascending memory boundaries, reading them back to determine the highest installed RAM address. On the standard trainer with a single 2KB 6116 SRAM, RAM ends at 17FFH. When extended with 6264 or 62256 chips, the full 64KB boundary is supported.
CHAPTER 2
Hardware & Front-Panel Tour
Anatomy of the molded beige chassis, PCB component layer, 7-segment display, tactile keypad matrix, speaker driver, and single-step circuit.
2.1 The Classic Molded Beige Console Enclosure
The ABC-80 is housed in a distinctive molded beige-cream structural plastic enclosure measuring 563 mm wide by 756 mm deep in scaled digital representation. A stepped rim and recessed well cradle the authentic double-sided drilled printed circuit board (Page 98 artwork). The front panel is inclined towards the operator for comfortable tactile keypad data entry.
2.2 Integrated Circuit Complement & Glue Logic
All ICs on the ABC-80 are socketed dual in-line packages (DIP) adhering to authentic 1980s specifications:
U1 (Z80A CPU): 40-pin DIP. Runs the Z80 instruction set with 158 instructions, dual register sets (AF/BC/DE/HL and AF'/BC'/DE'/HL'), index registers IX/IY, stack pointer SP, and program counter PC.
U2 & U3 (2716/2732 EPROMs): 24-pin DIP 600mil. U2 contains the 2KB Monitor ROM (0000H–07FFH). U3 provides the socket for expansion firmwares (0800H–0FFFH).
U4 (6116 SRAM): 24-pin DIP 600mil. High-speed 2K×8 static RAM holding user code, register save buffers, and stack.
U5 & U6 (8255A-5 PPIs): 40-pin DIP. U5 manages the human-machine interface; U6 manages the external daughterboard interface.
U7 (ZIF Socket): 28-pin levered Zero Insertion Force socket for programming 2716 and 2732 EPROMs.
U12 (74LS74): Dual D-type flip-flop used for clock frequency division and the hardware single-step wait generator.
2.3 6-Digit 7-Segment Multiplexed LED Display
The display consists of six red 7-segment LED displays arranged as four address digits (A3, A2, A1, A0) on the left and two data digits (D1, D0) on the right. Digit multiplexing is driven by 8255 PPI #1:
Port B (81H): Active-low segment anode bus (PB0=seg a, PB1=seg b, PB2=seg c, PB3=seg d, PB4=seg e, PB5=seg f, PB6=seg g, PB7=decimal point).
Port C (82H): Active-low digit cathode selection (PC0=A3, PC1=A2, PC2=A1, PC3=A0, PC4=D1, PC5=D0).
The Monitor ROM subroutines scd_k (04A6H) and scd_k1 (04CDH) sweep each cathode sequentially for approximately 1.5 ms, achieving a flicker-free refresh rate of ~110 Hz.
The audio output transducer (marked SP on the silkscreen) is an authentic 8Ω 0.25W ferro-magnetic dynamic speaker driven by a complementary push-pull transistor pair: Q7 (9013 NPN) and Q8 (9012 PNP). The speaker driver is tied directly to Port C bit 7 (PC7) of 8255 PPI #1 (pin 14). By toggling PC7 between high and low logic levels, the CPU creates clean, high-amplitude square waves without loading the digital bus.
2.5 Front-Panel LEDs & Single-Step Circuit
Indicator
Color
Circuit Source
Significance
EP
Red
Q1 / EPROM Vpp switch
Illuminated when high programming voltage (+21V/+25V) is applied to U7.
HALT
Red
Z80 pin 18 (/HALT)
Illuminated when the CPU executes opcode 76H and suspends bus activity.
SP-G
Green
74LS74 single-step gate
Indicates that the hardware single-step wait-state generator is armed.
CHAPTER 3
Keypad & Machine Code Tutorial
Cold reset, Address and Data operating modes, memory inspection, entering machine code, program termination, and register inspection.
3.1 Cold Boot & Hardware Reset
When power is applied or the red disc button (RST) is pressed, the CPU receives an active-low pulse on /RESET. The Z80 initializes PC = 0000H, configures 8255 PPI #1, performs memory sizing via ramchk, initializes the display buffer dspbf (13F2H–13F7H), and displays the welcome banner: ABC-80.
3.2 Operating Modes: Address Mode vs. Data Mode
The ABC-80 front panel operates in two primary input modes indicated by the display's decimal points:
Address Mode (ADRS): Press ADRS (or PC key A / M). All four decimal points on address digits A3. A2. A1. A0. illuminate. Hex keypad presses shift in from the right to form a 16-bit address (e.g. 1 0 0 0).
Data Mode (DATA): Press DATA (or PC key D). The two decimal points on data digits D1. D0. illuminate. Hex keypad presses shift in to form an 8-bit byte that is written directly into the current memory address in RAM.
Next Address (+): Press + (or PC key + / →). Increments the memory pointer by 1 and displays the byte stored at that location.
Single-Step Execution (-): Press - (or PC key - / F10). Triggers single-instruction execution through the 74LS74 wait-state gate.
3.3 Tutorial: Entering a Machine Code Program
Follow these exact steps to enter and run a test program that writes alternating patterns to Port B:
Press ADRS and enter 1 0 0 0. The display shows 1000 xx.
Press DATA. Decimal points appear under the data digits.
Enter 3 E (opcode for LD A, n), then press +. Address advances to 1001.
Enter 5 5 (immediate operand 55H), then press +. Address advances to 1002.
Enter D 3 (opcode for OUT (n), A), then press +. Address advances to 1003.
Enter 8 1 (Port B address 81H), then press +. Address advances to 1004.
Enter 1 8 (opcode for JR e), then press +. Address advances to 1005.
Enter F C (relative offset -4 to loop back to 1002H), then press +.
CRITICAL RULE: Re-Arm Address Before GO EXEC
After entering data or loading from cassette tape, the current address pointer points to the address after your last byte (e.g. 1006H). If you press GO EXEC immediately, the CPU will execute uninitialized memory and crash! Always press ADRS + 1 0 0 0 + GO EXEC!
3.4 Program Termination & Returning to Monitor
Instruction
Machine Code
Behavior
RST 38H
FF
Software breakpoint trap. Pushes PC to stack, vectors to 0038H, saves all CPU registers to RAM workspace, and restores the monitor prompt.
HALT
76
Suspends CPU bus activity. The HALT LED lights up. Press RST to recover.
JP 0070H
C3 70 00
Direct jump to the monitor warm-start entry point (entry1). Restores prompt without re-sizing RAM.
3.5 Inspecting CPU Registers in RAM Workspace
When returning to the Monitor via RST 38H or JP 0070H, all CPU registers are saved in a structured table in RAM (13CCH–13E3H). You can inspect and modify them using standard ADRS and DATA commands:
RAM Address
Register Pair
RAM Address
Register Pair
13CCH–13CDH
IX (low, high)
13D8H–13D9H
HL (L, H)
13CEH–13CFH
IY (low, high)
13DAH–13DBH
DE (E, D)
13D0H–13D1H
HL' alternate (L', H')
13DCH–13DDH
BC (C, B)
13D2H–13D3H
DE' alternate (E', D')
13DEH–13DFH
AF (F flags, A accum)
13D4H–13D5H
BC' alternate (C', B')
13E0H–13E1H
SP stack pointer
13D6H–13D7H
AF' alternate (F', A')
13E2H–13E3H
PC program counter
CHAPTER 4
Cassette Tape Storage (TO/FROM TAPE)
Kansas City / FSK audio modulation, 7-byte header format, recording and playback operating sequences, and checksum diagnostics.
4.1 Kansas City / FSK Audio Modulation Standard
The ABC-80 records digital machine code onto audio cassette tape using Frequency Shift Keying (FSK). The audio tone frequencies are derived directly from the Z80 CPU clock:
Leader Tone & Logic '0': 1.00 kHz square wave (8 half-periods per data bit).
Logic '1': 2.00 kHz square wave (16 half-periods per data bit).
Hardware Wiring: 8255 PPI #1 Port C bit 6 (PC6) drives the MIC audio output jack; Port A bit 7 (PA7) reads the Schmitt-trigger amplified EAR audio input jack.
4.2 Tape Frame Format & 7-Byte stepbf Header
Every cassette recording begins with ~1,000 cycles (1.0 s) of a 1 kHz leader tone, followed by an alignment sync byte (E6H), a 7-byte header buffer (stepbf at 17BFH), a 0.5 s inter-block tone, the data payload, and an 8-bit checksum byte:
Byte Offset
Buffer Field
Format
Description
00H–01H
File ID
16-bit little-endian
4-digit hex program identifier (e.g. 0001H–0103H)
02H–03H
Start Address
16-bit little-endian
Target memory load address (typically 1000H)
04H–05H
End Address
16-bit little-endian
Last memory address included in payload
06H
Header Checksum
8-bit arithmetic sum
Sum of bytes 00H through 05H modulo 256
4.3 Step-by-Step Walkthrough: TO TAPE (Saving Programs)
Place the Cassette Deck in record standby mode by clicking ● REC.
On the ABC-80 keypad, press TO TAPE (or PC key W). The display prompts for the File ID.
Enter the 4-digit hex File ID (e.g., 0 0 0 1).
Press ADRS and enter the 4-digit start address (e.g., 1 0 0 0).
Press ADRS and enter the 4-digit end address (e.g., 1 0 5 5).
Press GO EXEC. The CPU outputs the leader tone, sync byte, header block, payload data, and checksum. When finished, the Monitor returns to Address Mode.
4.4 Step-by-Step Walkthrough: FROM TAPE (Loading Programs)
In the Cassette Deck, enter the 4-digit File ID (e.g., 0001) and click ▶ PLAY. The reels turn and the 1 kHz tone begins streaming.
On the ABC-80 keypad, press FROM TAPE (or PC key L).
Enter the 4-digit File ID (e.g., 0 0 0 1).
Press GO EXEC.
The Monitor locks onto the leader tone, reads the header, flashes the File ID on the 6-digit display for ~1.5 seconds, streams the code into RAM, and stops at the end address in Data Mode.
Re-arm and execute: Press ADRS + 1 0 0 0 + GO EXEC!
4.5 Diagnostics: Checksum Error (-Err)
If tape audio is corrupted or audio volume is too low, the calculated 8-bit checksum will mismatch the recorded checksum. The Monitor aborts loading and displays -Err on the data digits. If this occurs, press RST, rewind the tape, and re-run the FROM TAPE sequence.
CHAPTER 5
Cassette Tape Program Catalog (All 33 Programs)
Complete laboratory library from 《Z80 微電腦入門 — 原理與應用程式》 (Labs 01–29) plus 4 custom interactive demonstration programs (Showcase 0100–0103).
Standard 3-Step Program Loading Procedure
Select Slot & Start Deck: In the Cassette Deck tab, pick the 4-digit File ID (or click Load Slot on any card below) and press ▶ PLAY.
Load via Monitor: On the ABC-80 keypad, press FROM TAPE + <d3><d2><d1><d0> + GO EXEC. Wait until the filename flashes and the end address appears in Data mode.
Hardware schematics, port assignments, and operating theory for the 6 modular peripheral daughterboards.
6.1 External Peripheral Interface Architecture
Exercises 24 through 29 interface the ABC-80 with physical external hardware experiments via 8255 PPI #2 and expansion bus connectors. The emulator provides high-fidelity interactive digital twin simulations for all six circuits, selectable from the EXT I/O dropdown in the board toolbar.
Wiring: PB0: NS Red, PB1: NS Yellow, PB2: NS Green; PB3: EW Red, PB4: EW Yellow, PB5: EW Green. Active-high logic.
Sequence: Cycles through North-South Green (0CH) $
ightarrow$ North-South Yellow blink (0AH) $
ightarrow$ All Red (08H) $
ightarrow$ East-West Green (21H) $
ightarrow$ East-West Yellow blink (11H) $
ightarrow$ All Red (01H).
DAC Network: Dual 4-bit R-2R resistor ladder DACs. Upper nibble (PB4–PB7) generates analog Y deflection (0–5V); lower nibble (PB0–PB3) generates analog X deflection (0–5V).
Sequence: Streams 37 coordinate pairs from RAM (1040H–1064H) at high speed, tracing geometric vector figures on an oscilloscope in X-Y Lissajous mode.
6.5 Exercise 27: School Bell Clock & Relay (實習 27：校鐘)
Port: 8255 #1 Port C (82H).
Relay Circuit: Bit 6 (PC6) controls an NPN transistor driving an electromechanical bell relay coil (active-low).
Sequence: 24-hour BCD clock display. When minutes match :00 or :10 for hours $\ge 08:00$, the relay energizes and an 8-note melodic chime plays on the speaker.
6.6 Exercise 28: Automated Home Appliance Timer (實習 28：家庭電器電腦化控制)
Port: Auxiliary 8255 #2 Port C (42H).
Relay Outputs: Controls 8 independent 110V/220V AC relays for lighting, water heaters, air conditioners, and irrigation pumps.
Sequence: Compares current 24-hour time against a 37-byte programmable schedule table at 1100H–1124H to automatically switch loads on and off.
6.7 Exercise 29: 3-Axis Robotic Arm & Gripper (實習 29：模擬機械手)
Ports: Expansion 8255: Port 00H (Base rotation), Port 01H (Shoulder elevation), Port 02H (Elbow/Wrist & Solenoid clamp).
Drive Scheme: 4-phase unipolar stepper motor drive sequences with half-step and full-step tables at 1100H–1173H.
Sequence: Executes repeatable automated pick-and-place trajectories, picking objects and transferring them to designated drop zones.
CHAPTER 7
QuickBASIC 4.0 PC-Link & CRT
1993 PC/AT host connection, parallel handshake protocol on ports C0H–C3H, resident server loop at 0B00H, and CRT monitor controls.
7.1 The 1993 QuickBASIC 4.0 PC-Link Heritage
In 1993, Charles Chiou developed a custom EPROM replacement for the ABC-80 that connected the trainer to an IBM PC/AT clone running Microsoft QuickBASIC 4.0. Using an 8255 parallel handshake cable, the PC acts as a smart host terminal, enabling high-speed assembly uploading, memory editing, and disassembling on a color VGA CRT monitor.
7.2 Connecting the Emulated PC/AT CRT Terminal
In the board toolbar, change the ROM selector to Charles Chiou's ROM (1993). The trainer power-cycles and displays 009B.
In the main header, click the PC/AT CRT button to open the floating early-'90s VGA CRT window.
Press F1 to initiate the hardware handshake. The CRT displays ABC-80 SYSTEM READY and establishes communication with the server loop running at 0B00H.
7.3 QuickBASIC Environment Hotkeys
Command
Key
Description
Connect
F1
Establish bidirectional parallel handshake with the ABC-80 CPU.
ADDs
A
Set the starting memory address pointer for display and entry.
Data
D
Enter machine code bytes into the target RAM buffer.
INS
I
Insert a byte into the current memory address, shifting subsequent bytes.
DEL
X
Delete a byte from the current memory address, shifting subsequent bytes.
Run
R
Execute the machine code program starting at the active address.
Exit
Shift+Esc
Exit PC-Link and return execution to the ABC-80 standalone keypad prompt (009BH).
CHAPTER 8
Monitor ROM & Memory Reference
Authoritative memory map, RAM workspace variables, Monitor ROM API subroutines, and 7-segment hex glyph encoding table.
8.1 Complete Memory Map Reference (0000H–FFFFH)
Address Range
Size
Device
Description
0000H–07FFH
2048 B
2716 EPROM (U2)
Resident Monitor ROM (Reset vectors, keypad, display, cassette tape)
0800H–0FFFH
2048 B
2716/32 EPROM (U3)
Expansion ROM socket (QuickBASIC PC-Link or user custom ROM)
1000H–13CBH
972 B
6116 SRAM (U4)
User program RAM area (standard load address for all labs)
13CCH–13E3H
24 B
6116 SRAM (U4)
CPU saved register workspace (IX, IY, HL', DE', BC', AF', HL, DE, BC, AF, SP, PC)
13E4H–17FAH
1047 B
6116 SRAM (U4)
Monitor system buffers, display buffer (dspbf), and tape buffers
17FBH–17FFH
5 B
6116 SRAM (U4)
Hardware monitor stack area (top of onboard 2KB SRAM)
1800H–FFFFH
59392 B
Expansion RAM
Optional extended memory space dynamically probed by ramchk (06DCH)
